AI01020
13
A0-A12
W
DQ0-DQ7
VCC
M48T08
M48T18
G
E2
VSS
8
E1
INT
Figure 1. Logic Diagram
M48T08
M48T18
CMOS 8K x 8 TIMEKEEPER SRAM
INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK and POWER-FAIL
CONTROL CIRCUIT
BYTEWIDE RAM-LIKE CLOCK ACCESS
BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES and SECONDS
CLOCK ACCURACY of
1 MINUTE a
MONTH, @ 25
C
SOFTWARE CONTROLLED CLOCK
CALIBRATION for HIGH ACCURACY
APPLICATIONS
AUTOMATIC POWER-FAIL CHIP DESELECTand
WRITE PROTECTION
CHOICE of TWO WRITE PROTECT
VOLTAGES:
M48T08: 4.5V
V
PFD
4.75V
M48T18: 4.2V
V
PFD
4.5V
SELF CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
SMALL OUTLINE PACKAGE PROVIDES
DIRECT CONNECTION for a SNAPHAT
HOUSING CONTAINING the BATTERY and
CRYSTAL
SNAPHAT HOUSING (BATTERY and
CRYSTAL) REPLACEABLE
10 YEARS of DATA RETENTION and CLOCK
OPERATION in the ABSENCE of POWER
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 8K x 8 SRAMs
A0-A12
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
INT
Power Fail Interrupt
E1
Chip Enable 1
E2
Chip Enable 2
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
28
1
PCDIP28 (PC)
Battery CAPHAT
28
1
SOH28 (MH)
Battery SNAPHAT
November 1994
1/18
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
C
T
STG
Storage Temperature (V
CC
Off, Oscillator Off)
40 to 85
C
V
IO
Input or Output Voltages
0.3 to 7
V
V
CC
Supply Voltage
0.3 to 7
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability.
CAUTION: Negative undershoots below 0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 2. Absolute Maximum Ratings
Mode
V
CC
E1
E2
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
X
High Z
Standby
Deselect
X
V
IL
X
X
High Z
Standby
Write
V
IL
V
IH
X
V
IL
D
IN
Active
Read
V
IL
V
IH
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
X
X
X
X
High Z
CMOS Standby
Deselect
V
SO
X
X
X
X
High Z
Battery Back-up Mode
Note: X = V
IH
or V
IL
Table 3. Operating Modes
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
E2
A10
A8
A9
DQ7
W
A11
G
E1
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
INT
VCC
AI01182
M48T08
M48T18
8
1
2
3
4
5
6
7
9
10
11
12
13
14
16
15
28
27
26
25
24
23
22
21
20
19
18
17
Figure 2A. DIP Pin Connections
AI01021B
8
2
3
4
5
6
7
9
10
11
12
13
14
22
21
20
19
18
17
16
15
28
27
26
25
24
23
1
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
E2
A10
A8
A9
DQ7
W
A11
G
E1
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
INT
VCC
M48T08
M48T18
Figure 2B. SO Pin Connections
2/18
M48T08, M48T18
AI01019
5V
OUT
CL = 100pF
CL includes JIG capacitance
1.8k
DEVICE
UNDER
TEST
1k
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
AC MEASUREMENT CONDITIONS
Note that Output Hi-Z is defined as the point where data
is no longer driven.
AI01333
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VPFD
INT
VCC
VSS
32,768 Hz
CRYSTAL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
8 x 8 BiPORT
SRAM ARRAY
8184 x 8
SRAM ARRAY
A0-A12
DQ0-DQ7
E1
E2
W
G
POWER
Figure 3. Block Diagram
DESCRIPTION
The M48T08,18 TIMEKEEPER
TM
RAM is an 8K x 8
non-volatile static RAM and real time clock which
is pin an d fu nctional compatible with the
MK48T08,18. The monolithic chip is available in
two special packages to provide a highly integrated
battery backed-up memory and real time clock
solution.
The M48T08,18 is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The 28 pin 600mil DIP CAPHAT
TM
houses the
M48T08,18 silicon with a quartz crystal and a long
life lithium button cell in a single package.
The 28 pin 330mil SO provides sockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT
TM
housing containing the
battery and crystal. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SO package after the completion of the
surface mount process.
3/18
M48T08, M48T18
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
(1)
Input Leakage Current
0V
V
IN
V
CC
1
A
I
LO
(1)
Output Leakage Current
0V
V
OUT
V
CC
5
A
I
CC
Supply Current
Outputs open
80
mA
I
CC1
(2)
Supply Current (Standby) TTL
E1 = V
IH
, E2 = V
IL
3
mA
I
CC2
(2)
Supply Current (Standby) CMOS
E1 = V
CC
0.2V,
E2 = V
SS
+ 0.2V
3
mA
V
IL
(3)
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
Output Low Voltage (INT)
(4)
I
OL
= 0.5mA
0.4
V
V
OH
Output High Voltage
I
OH
= 1mA
2.4
V
Notes: 1. Outputs Deselected.
2. Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0'.
3. Negative spikes of 1V allowed for up to 10ns once per Cycle.
4. The INT pin is Open Drain.
Table 5. DC Characteristics (T
A
= 0 to 70
C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
10
pF
C
IO
(2)
Input / Output Capacitance
V
OUT
= 0V
10
pF
Notes: 1. Effective capacitance calculated from the equation C = I
t/
V with
V = 3V and power supply at 5V.
2. Outputs deselected
Table 4. Capacitance
(1)
(T
A
= 25
C, f = 1 MHz )
Symbol
Parameter
Min
Typ
Max
Unit
V
PFD
Power-fail Deselect Voltage (M48T08)
4.5
4.6
4.75
V
V
PFD
Power-fail Deselect Voltage (M48T18)
4.2
4.3
4.5
V
V
SO
Battery Back-up Switchover Voltage
3.0
V
t
DR
(2)
Expected Data Retention Time
10
YEARS
Notes: 1. All voltages referenced to V
SS
.
2. @ 25
C
Table 6. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70
C)
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is keyed to
prevent reverse insertion.
The SO and battery packages are shipped sepa-
rately in plastic anti-static tubes. The SO package
is also available to ship in Tape & Reel form. For
the 28 lead SO, the battery package (i.e.
SNAPHAT) part number is "M4T28-BR12SH1".
As Figure 3 shows, the static memory array and the
quartz controlled clock oscillator of the M48T08,18
are integrated on one silicon chip. The two circuits
are interconnected at the upper eight memory lo-
cations to provide user accessible BYTEWIDE
TM
clock information in the bytes with addresses
1FF8h-1FFFh. The clock locations contain the
year, month, date, day, hour, minute, and second in
DESCRIPTION (cont'd)
4/18
M48T08, M48T18
Symbol
Parameter
Min
Max
Unit
t
PD
E1 or W at V
IH
or E2 at V
IL
before Power Down
0
s
t
F
(1)
V
PFD
(max) to V
PFD
(min) V
CC
Fall Time
300
s
t
FB
(2)
V
PFD
(min) to V
SO
V
CC
Fall Time
10
s
t
R
V
PFD
(min) to V
PFD
(max) V
CC
Rise Time
0
s
t
RB
V
SO
to V
PFD
(min) V
CC
Rise Time
1
s
t
REC
E1 or W at V
IH
or E2 at V
IL
after Power Up
1
ms
t
PFX
INT Low to Auto Deselect
10
40
s
t
PFH
(3)
V
PFD
(max) to INT High
120
s
Notes: 1. V
PFD
(max) to V
PFD
(min) fall time of less than t
F
may result in deselection/write protection not occurring until 200
s after
V
CC
passes V
PFD
(min).
2. V
PFD
(min) to V
SO
fall time of less than t
FB
may cause corruption of RAM data.
3. INT may go high anytime after V
CC
exceeds V
PFD
(min) and is guaranteed to go high t
PFH
after V
CC
exceeds V
PFD
(max).
Table 7. Power Down/Up Mode AC Characteristics (T
A
= 0 to 70
C)
AI00566
VCC
INPUTS
INT
(PER CONTROL INPUT)
OUTPUTS
DON'T CARE
HIGH-Z
tF
tFB
tPFX
tR
tPFH
tREC
tPD
tRB
tDR
VALID
VALID
NOTE
(PER CONTROL INPUT)
RECOGNIZED
RECOGNIZED
VPFD (max)
VPFD (min)
VSO
Figure 5. Power Down/Up Mode AC Waveforms
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1high or E2 low as V
CC
rises past V
PFD
(min).
Some systems may performs inadvertent write cycles after V
CC
rises above V
PFD
(min) but before normal system operations begins. Even
though a power on reset is being applied to the processor a reset condition may not occur until after the system clock is running.
5/18
M48T08, M48T18
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